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Multiprocessor system on chip is a concept that aims to integrate multiple hardware and software in a chip. multistage interconnection network is considered as a promising solution for applications which use parallel architectures integrating a large number of processors and memories. in this paper, we present a model of multistage interconnection network and a design of prototyping on FPGA. This enabled the comparison of the proposed model with the full crossbar network, and the estimation of performance in terms of area, latency and energy consumption. The Multistage Interconnection Networks are well adapted to MPSoC architecture. They meet the needs of intensive signal processing and they are scalable to connect a large number of modules.