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Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications

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1 Author(s)
Meher, P.K. ; Inst. for Infocomm Res., Singapore

In this paper, we present a new approach for the extension of sequential logic functionality of D flip-flop in order to perform an additional Boolean function simultaneously along with its usual bit-storage function. We show that a combinational function of the form (a middotb), (a + b) , (a +[(b)]), or ([(a)] middotb) which occurs frequently in a feedforward path with a D flip-flop could be implemented efficiently by a D flip-flop with RESET or SET provision. Similarly, (a oplusb) or ((a middotb) oplusc) in the feedback loop with a D flip-flop could be implemented by a T flip-flop by suitable modification of the clock. The use of such extended sequential logic is found to result in a significant reduction in critical path and saving in area complexity over the direct implementation. Moreover, we present a simple approach for the construction of CMOS T flip-flop by modification of clock signal of D flip-flop, which is found to be more efficient than the T flip-flop derived from JK flip-flop. The extended sequential logic is used for the implementation of finite-field multiplication over GF(2m) and carry-save addition of real numbers. In both these cases, the use of extended logic is found to offer a substantial saving in area and time complexity over the conventional implementations.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:28 ,  Issue: 4 )