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Functional test generation for delay faults in combinational circuits

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2 Author(s)
I. Pomeranz ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; S. M. Reddy

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. It can also potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of branch and bound strategies. A parameter called /spl Delta/ is used to control the number of functional faults targeted and thus the number of tests generated. If /spl Delta/ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given function. An appropriate subset of tests can be selected once the implementation is known. The test sets generated for various values of /spl Delta/ are fault simulated on gate-level realizations to demonstrate their effectiveness.

Published in:

Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on

Date of Conference:

5-9 Nov. 1995