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A delay model for logic synthesis of continuously-sized networks

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5 Author(s)
Grodstein, J. ; Digital Equipment Corp., Hudson, MA, USA ; Lehman, E. ; Harkness, H. ; Grundmann, B.
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We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as constant and makes the cell's delay a linear function of load. Out model is based on a different, but equally fundamental linearity in the equation relating area, delay, and load: namely, we may keep a cell's delay constantly making its area a linear function of load. This allows us to technology map using a library with continuous device sizing, satisfies certain electrical noise and power constraints, and in certain cases is computationally simpler than a traditional model. We give results to support these claims. A companion paper uses the computational simplicity to explore a wide search space of algebraic factorings in a mapped network.

Published in:

Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on

Date of Conference:

5-9 Nov. 1995