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Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs

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2 Author(s)
Victor Dumitriu ; Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada ; Gul N. Khan

This paper presents a new approach to the design and analysis of NoC topologies which is based on the transaction-oriented communication methods of on-chip components. We propose two algorithms that attempt to meet the communication requirement of an on-chip application using a minimum number of network resources for the task, by generating application-specific topologies. In addition, to aid the design process of complex systems, the design method incorporates a form of predictive analysis which can estimate the degree of contention in a given system without performing detailed simulation. This predictive analysis method is used to determine the minimum frequency of operation for generated topologies, and is incorporated into the topology generation process. The proposed design method was tested using real-word applications, including an MPEG4 decoder and a multi-window display application. The generated topologies were found to offer similar or better performance when compared with regular topologies. However, the topologies generated by our method were more economical, using, on average, half the network resources of regular topologies.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:17 ,  Issue: 10 )