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Scaling, Power, and the Future of CMOS Technology

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1 Author(s)
Horowitz, M. ; Room 306, Gates Computer Science Building, 353 Serra Mall, Stanford, CA 94305, Ph: (650)725-3707, FAX: (650)725-6949, Email: horowitz@ee.stanford.edu

Over 40 years ago, Gordon Moore wrote a short paper that has come to define this industry. In addition to the prediction that IC device counts would grow exponentially, this paper also described three main challenges to scaling: power, design cost, and what to do with the available functionality. While we have found good uses for the added functionality, power and design cost remain critical issues today, and with the ending of Dennard scaling, power looms as the largest challenge in our ability to continue to scale computing performance. This talk looks briefly at the origins of this power crisis, and then explores architectural and circuit approaches to produce energy efficient designs. The results have some interesting implications for device design.

Published in:

Device Research Conference, 2008

Date of Conference:

23-25 June 2008