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With the increase of clock speeds, clock skew has become a significant part of the cycle time of high speed microprocessors. While many clock tree routing techniques promise zero or minimal skew, algorithm assumptions or design methodology constraints often prevent a single approach from being suitable for the entire clock design. In this paper we describe a collection of strategies for designing low skew clock distributions. These techniques are applied at various levels of design (synthesis, placement, routing etc.) to yield clock distribution networks of acceptable skew for the two different clock design styles used by PowerPC processors. We also describe a static timing based approach for analyzing the clock network to detect the various clock violations of interest. Finally we outline current deficiencies in our methodology.