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This paper presents measured, simulated and calculated third-order intercept point (IP3) on a 90-nm RF CMOS technology. The IP3 sweet spot is actually at a V GS lower than zero K 3g m point. This V GS difference is attributed to the nonlinear output conductance and the cross terms using a Volterra-series-based IP3 expression. The impact of these nonlinearities is quantified using simulated I-V and device small-signal parameters extracted from S -parameter simulation. The scaling factors of the nonlinearities causes a decrease of IP3 sweet spot J DS as device size increases. The IP3 expression can accurately predicts the device size dependence of IP3 sweet spot. The frequency dependence of IP3 is determined by the small signal capacitance. Thus, the frequency dependence is very weak and negligible for a small device. For a large device, not only gate-source capacitance and drain-bulk capacitance, but also gate-drain capacitance are important. To determine the value of IP3 accurately, a more complete equivalent circuit of the MOS transistor must be used in Volterra-series analysis. The V DS dependence of the IP3 sweet spot V GS is primarily due to drain induced barrier lowering.