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A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

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6 Author(s)
Liang Zhang ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA ; John M. Wilson ; Rizwan Bashirullah ; Lei Luo
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This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:17 ,  Issue: 9 )