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A programmable rational-K/L frequency multiplier that can synthesize any frequency between 25 MHz and 6 GHz from an input clock ranging from 1 to 5.5 GHz is presented. The architecture employs a fractional-N input clock divider followed by a fractional- N PLL. In contrast to conventional architectures, this allows large K and L, whose maximum values are limited only by the word-length of digital SigmaDelta modulators. Additionally, to alleviate large K vco variation and fractional spurs, which are inevitable in wide tuning range VCOs and fractional-N synthesizers, new compensation techniques are implemented without involving additional circuitry. This is an ideal solution to support a programmable serializer/deserializer on a field-programmable gate array.