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High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms

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2 Author(s)
N. Kroupis ; Department of Electrical and Computer Engineering, Democritus University of Thrace, 67 100 Xanthi, Greece E-mail: ; D. Soudris

Considering the time-to-market restrictions and the increased computational complexity of modern applications, the efficient design of data intensive digital signal processing (DSP) applications is a challenging problem. A typical design exploration procedure, which uses simulation-based tools for various cache parameters, is a rather time-consuming task, even for low-complexity applications. The main goal is the introduction of a novel estimation methodology, which provides fast and accurate estimates of the number of executed instructions and the instruction cache miss rate of data intensive applications implemented on a programmable embedded platform, during the early design phases. The proposed methodology consists of three stages, where the first one is a platform-independent stage, whereas the remaining two use information from the chosen embedded platform. In particular, specific information is extracted from both the high-level code description (C code) of the application and its corresponding assembly code, without carrying out any kind of simulation. The proposed methodology requires only a single execution of the application in a general-purpose processor and uses only the assembly code of the targeted embedded processor. To accelerate the estimation procedure, a novel software tool, which implements the proposed methodology, has been developed. Using nine real-life data intensive applications from different domains of the DSP field, it has been proved that with the proposed methodology the number of instructions and the miss rate of the instruction cache can be estimated with very high accuracy (>90%). Furthermore, the required time cost is much smaller (orders of magnitude) than the existing simulation-based approaches.

Published in:

IET Computers & Digital Techniques  (Volume:3 ,  Issue: 2 )