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Statistical Design of the 6T SRAM Bit Cell

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2 Author(s)
Gupta, V. ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada ; Anis, M.

In this paper, a method for the statistical design of the static-random-access-memory bit cell is proposed to ensure a high memory yield while meeting design specifications for performance, stability, area, and leakage. The method generates the nominal design parameters, i.e., the widths and lengths of the bit-cell transistors, which provide maximum immunity to the variations in a transistor's dimensions and intrinsic threshold-voltage fluctuations. Moreover, the need to deviate from the conventional bit-cell sizing strategy to obtain a high-yield low-leakage design in the nanometer regime is demonstrated.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:57 ,  Issue: 1 )