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A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

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11 Author(s)
Tyler L. Brandon ; Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada ; John C. Koob ; Leendert van den Berg ; Zhengang Chen
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We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process. The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. The decoder design uses a memory-based interface with a minimum number of memory banks to deliver an information throughput of 1 b per clock cycle. The decoder shares one controller among a pipeline of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2 dB and a decoded throughput of 600 Mb/s. On-chip test circuitry permits accurate power measurements to be made at selectable SNR settings.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:56 ,  Issue: 5 )