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Implementation and optimization of asymmetric transistors in advanced SOI CMOS technologies for high performance microprocessors

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21 Author(s)
Hoentschel, J. ; AMD Fab 36 LLC & Co. KG, Dresden ; Wei, A. ; Wiatr, M. ; Gehring, A.
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Sub-40 nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12% and 10%, respectively, resulting in performance at 1.0 V and 100 nA/mum IOFF of NIDSAT=1354 muA/mum and PIDSAT=857 muA/mum. Product-level implementation of asymmetric transistors showed a speed benefit of 12%, at matched yield and improved reliability.

Published in:

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Date of Conference:

15-17 Dec. 2008