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A low power 40nm CMOS technology featuring extremely high density of logic (2100kGate/mm2) and SRAM (0.195μm2) for wide range of mobile applications with wireless system

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29 Author(s)
Watanabe, R. ; Syst. LSI Div., Toshiba Corp., Yokohama ; Oishi, A. ; Sanuki, T. ; Kimijima, H.
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Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum2 SRAM with excellent static noise margin is also accomplished by minimizing random impurity fluctuation using Hf doped silicate as gate dielectrics. In addition, novel DFM (Design for Manufacturing) techniques are introduced for systematic yield improvement.

Published in:

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Date of Conference:

15-17 Dec. 2008