By Topic

A low power 40nm CMOS technology featuring extremely high density of logic (2100kGate/mm2) and SRAM (0.195μm2) for wide range of mobile applications with wireless system

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

29 Author(s)
R. Watanabe ; System LSI Division, Semiconductor Company, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan ; A. Oishi ; T. Sanuki ; H. Kimijima
more authors

Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum2 SRAM with excellent static noise margin is also accomplished by minimizing random impurity fluctuation using Hf doped silicate as gate dielectrics. In addition, novel DFM (Design for Manufacturing) techniques are introduced for systematic yield improvement.

Published in:

2008 IEEE International Electron Devices Meeting

Date of Conference:

15-17 Dec. 2008