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32nm general purpose bulk CMOS technology for high performance applications at low voltage

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36 Author(s)
Arnaud, F. ; STMicroelectronics, IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY ; Liu, J. ; Lee, Y.M. ; Lim, K.Y.
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This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um2 SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.

Published in:

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Date of Conference:

15-17 Dec. 2008