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Experimental and theoretical analysis of factors causing asymmetrical temperature dependence of Vt in High-k Metal gate CMOS with capped High-k techniques

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2 Author(s)
Iijima, R. ; IBM TJ Watson Res. Center, Toshiba America Electron. Components Inc., Yorktown Heights, NY ; Takayanagi, M.

Temperature (T) dependence of threshold voltage (Vt) for high-k metal gate stack (HK/MG) CMOS is investigated thoroughly. It is found, for the first time, that T dependence of Vt (dVt/dT) for HK/MG CMOS shows asymmetrical behavior between N and PFETs unlike conventional Poly-Si/SiON CMOS. Moreover, this dVt/dT asymmetry is observed even if capping techniques for Vt tuning are applied to high-k dielectrics. The position of effective Fermi level in HK/MG (EFM,eff) is determined quantitatively in a wide range of T by experimental and theoretical analysis for the first time, which reveals that the off-center arrangement of EFM,eff in Si band gap is the cause of dVt/dT asymmetry not only in the long channel region but also in the short channel region. In addition, based on these analyses, dVt/dT for aggressively thinned FinFETs with HK/MG is predicted.

Published in:

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Date of Conference:

15-17 Dec. 2008