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Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and high-k/metal gate stack for monolithic 3D integration

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7 Author(s)
Jin-Hong Park ; Department of Electrical Engineering, CIS, Stanford University, Stanford, CA, 94305, USA ; Munehiro Tada ; Duygu Kuzum ; Pawan Kapur
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We demonstrate high performance, 3D IC compatible, Ge n and p-MOSFETs fabricated at very low temperatures, below 380degC. The low temperature gate stack comprises of high-K/metal materials. Very low series resistance (2.23times10-4 Omega-cm at the lowest point of SRP) and shallow (92 nm) source/drain (S/D) junctions with high degree of dopant activation is achieved especially in n-MOSFETs using CMOS process compatible technique - metal (Co) induced dopant activation (Co MIDA) and Ge crystallization. Low S/D resistance in Ge n-MOSFETs has previously been highly challenging. The Ge n-MOSFET, fabricated at 360degC, has an electron mobility comparable to the highest one reported previously, while the Ge p-MOSFET shows a hole mobility higher than the universal Si mobility. The Ge n- and p-MOSFETs provide an excellent Ion/Ioff ratio ( ~1.1times103 for both). In addition to other uses, this low temperature Ge CMOS process serves as a compelling enabler for integrating high performance Ge transistors above metal layers as required by 3D-ICs without exceeding 400degC.

Published in:

2008 IEEE International Electron Devices Meeting

Date of Conference:

15-17 Dec. 2008