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IO connection assignment and RDL routing for flip-chip designs

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2 Author(s)
Jin-Tai Yan ; Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan, R.O.C. ; Zhi-Wei Chen

Given a set of IO buffers and bump balls with the capacity constraints between bump balls, an O(n2) IO assignment and RDL routing algorithm is proposed to assign all the IO connections and minimize the total wirelength with satisfying the capacity constraints and guarantee 100% routability if the capacity constraint is permitted, where n is the number of bump balls in a flip-chip design. Compared with the combination of the greedy IO assignment and our RDL routing, our IO assignment reduces the global wirelength by 7.6% after global routing and improves the routability by 8.8% after detailed routing on the average. Compared with the combination of our IO assignment, the single-layer BGA global router[8] and our detailed routing phase, our RDL routing reduces the global wirelength by 15.9% after global routing and improve the routability by 10.6% after detailed routing on the average for some tested circuits in reasonable CPU time.

Published in:

2009 Asia and South Pacific Design Automation Conference

Date of Conference:

19-22 Jan. 2009