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A dual-mode baseband (W-CDMA/HSDPA and GSM/GPRS/EDGE) and multimedia application processor SoC is described. The SoC fabricated in triple-Vth 65 nm CMOS has 3 CPU cores and 20 separate power domains to achieve both high performance and low power. The SoC adopts the partial clock activation scheme that reduces power by 42% for long-time music replay. The IP-MMU is introduced to reduce maximum memory footprint by 43 MB, sharing external memory among CPUs and HW-IPs using virtual address space that enables reuse of physically fragmented memory.
Date of Conference: 19-22 Jan. 2009