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A multilevel analytical placement for 3D ICs

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2 Author(s)
Cong, J. ; Comput. Sci. Dept., Univ. of California, Los Angeles, CA ; Guojie Luo

In this paper we propose a multilevel non-linear programming based 3D placement approach that minimizes a weighted sum of total wirelength and TS via number subject to area density constraints. This approach relaxes the discrete layer assignments so that they are continuous in the z-direction and the problem can be solved by an analytical global placer. A key idea is to do the overlap removal and device layer assignment simultaneously by adding a density penalty function for both area & TS via density constraints. Experimental results show that this analytical placer in a multilevel framework is effective to achieve trade-offs between wirelength and TS via number. Compared to the recently published transformation-based 3D placement method, we are able to achieve on average 12% shorter wirelength and 29% fewer TS via compared to their cases with best wirelength; we are also able to achieve on average 20% shorter wirelength and 50% fewer TS via number compared to their cases with best TS via numbers.

Published in:

Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific

Date of Conference:

19-22 Jan. 2009