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Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications

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3 Author(s)
Pasricha, S. ; Univ. of California, Irvine, CA ; Dutt, N. ; Kurdahi, F.J.

The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Most traditional on-chip communication architecture design techniques perform synthesis and optimization only for a single use-case, which may lead to sub-optimal design decisions for multi-use case applications. In this paper we present a framework to generate a dynamically reconfigurable crossbar-based on-chip communication architecture that can support multiple use-case bandwidth and latency constraints. Our framework generates on-chip communication architectures with a low cost, low power dissipation, and with minimal reconfiguration overhead. Results of applying our framework on several networking CMP applications show that our approach is able to generate a crossbar solution with significantly lower cost (2.4times to 3.8times), and lower power dissipation (1.5times to 3.1times), compared to the best previously proposed approach.

Published in:

Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific

Date of Conference:

19-22 Jan. 2009

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