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High multiplication factor capacitor multiplier for an on-chip PLL loop filter

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5 Author(s)
Choi, J. ; Georgia Electron. Design Center, Georgia Inst. of Technol., Atlanta, GA ; Park, J. ; Kim, W. ; Lim, K.
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A capacitor multiplier with a high multiplication factor and low power consumption is proposed to integrate a large capacitor of a phase-locked loop (PLL) filter in a small chip area. The proposed capacitor multiplier makes capacitance of 516.8 pF using an on-chip capacitor of 7.95 pF with current consumption of 100 A. An integer-N PLL with a channel space of 1 MHz was fabricated with a 0.18 m CMOS technology to employ the proposed capacitor multiplier.

Published in:

Electronics Letters  (Volume:45 ,  Issue: 5 )

Date of Publication:

February 26 2009

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