By Topic

Thermal Modeling and Device Noise Properties of Three-Dimensional–SOI Technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Tze Wee Chen ; Center for Integrated Syst., Stanford Univ., Stanford, CA ; Jung-Hoon Chun ; Yi-Chang Lu ; Reza Navid
more authors

Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-mum three-dimensional (3-D)-SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D-SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D-SOI technology are also characterized and compared with conventional bulk CMOS technology.

Published in:

IEEE Transactions on Electron Devices  (Volume:56 ,  Issue: 4 )