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Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA

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2 Author(s)
Chun-Lung Hsu ; Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien ; Ting-Hsuan Chen

This paper presents a built-in self-test (BIST) design for fault detection and fault diagnosis of static-RAM (SRAM)-based field-programmable gate arrays (FPGAs). The proposed FPGA BIST structure can test both the interconnect resources [wire channels and programmable switches (PSs)] and lookup tables (LUTs) in the configurable logic blocks (CLBs). The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The target fault detection/diagnosis of the proposed BIST structure are open/short and delay faults in the wire channels, stuck on/off faults in PSs, and stuck-at-0/1 faults in LUTs. The applications on XC4000-series FPGAs show that 100% fault coverage of the proposed FPGA BIST structure can be obtained. Additionally, the test results reveal that good performance in fault detection and fault diagnosis on both interconnect resources and CLBs can be achieved at levels similar to those required in previous works.

Published in:

Instrumentation and Measurement, IEEE Transactions on  (Volume:58 ,  Issue: 7 )

Date of Publication:

July 2009

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