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Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency

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3 Author(s)
Xiaoyao Liang ; Harvard Univ., Cambridge, MA ; Gu-Yeon Wei ; Brooks, D.

Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a single chip, and microarchitectural blocks within one core. The revival technique combines the post-fabrication tuning techniques voltage interpolation (VI) and variable latency (VL) to reduce such frequency variations.

Published in:

Micro, IEEE  (Volume:29 ,  Issue: 1 )