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Time-area efficient multiplier-free filter architectures for FPGA implementation

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3 Author(s)
Shajaan, M. ; Electron. Inst., Tech. Univ. Denmark, Lyngby, Denmark ; Nielsen, K. ; Sorensen, J.A.

Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is 𝒪 (filter order). The hardware design methodology leads to high performance filters with sampling frequencies in the interval 20-50 MHz. Time-area efficiency and performance of the architectures are considerably above any known approach

Published in:

Acoustics, Speech, and Signal Processing, 1995. ICASSP-95., 1995 International Conference on  (Volume:5 )

Date of Conference:

9-12 May 1995

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