By Topic

PSEUDEC: implementation of the computation-intensive PARTRAN functionality using a dedicated on-line CORDIC co-processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
F. T. Moller ; Inst. for Electron. Syst., Aalborg Univ., Denmark ; J. B. Andersen ; H. R. Jensen ; O. Olsen
more authors

This paper describes PSEUDEC, a dedicated co-processor and the rationale behind its design. The final goal of our work is to present a single chip solution with low power consumption for an advanced digital hearing aid based on a parameterized transformation of speech (PARTRAN). Characterization of the constituent parts of the PARTRAN algorithm shows that it is well suited for implementation on a heterogeneous architecture. The design strategy used identifies a subset for implementation on dedicated hardware, with a computational complexity roughly equivalent to the performance of a standard 10 MIPS DSP. The subset of PARTRAN implemented by PSEUDEC performs pseudo-decomposition of a 12th order LPC polynomial. An adapted algorithm displays improved dynamic range compared to the conventional solution for DSPs, calculating the amplitude spectrum rather than the power spectrum. Highly pipelined CORDIC-units optimized for the application replaces complex multiplication, trigonometric operations (for e) and square root (for |a|=√(ar2+ai2)), exploiting the power of CORDIC operations in advanced DSP algorithms. PSEUDEC uses redundant data representation and bit-serial arithmetic, most significant digit first (on-line arithmetic) for efficient implementation of operators and for efficient (inter-operator) communication. The inherent nature of on-line arithmetic and the operators used allows for fast and efficient implementation even when using ordinary standard cells

Published in:

Acoustics, Speech, and Signal Processing, 1995. ICASSP-95., 1995 International Conference on  (Volume:5 )

Date of Conference:

9-12 May 1995