By Topic

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Lan-Chou Cho ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei ; Chihun Lee ; Chao-Ching Hung ; Shen-Iuan Liu

A 33.6-33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 11 -1 PRBS. The measured bit error rate is less than 10-8 for a 33.72 Gb/s, 27 -1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 3 )