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This paper introduces a hybridized version of two common topologies of LC-based clock buffers. The proposed design can minimize jitter by adaptively adjusting the ratio between these two topologies. The analysis shows that the setting for optimum jitter depends on the relative level between the input noise and the inherent noise of the clock buffer. The long-term and short-term jitters are both studied and supported by measurement. A frequency tuning technique based on a voltage-swing digitizer is also demonstrated. The test chip is fabricated in a 1P8M 1.2-V 0.13-mum digital CMOS process. The power consumption of the proposed LC-based clock buffer is 12 mW.