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Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

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9 Author(s)
Nii, K. ; Renesas Technol. Corp., Itami ; Tsukamoto, Y. ; Yabuuchi, M. ; Masuda, Y.
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We propose an access scheme for a synchronous dual- port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bit- line access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 mum2 8T-DP-cell for which the cell size is only 1.44 times larger than a 6T-single-port (SP)- cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm2, which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

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Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 3 )