Cart (Loading....) | Create Account
Close category search window

A Single–Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and {+} 90 dBm IIP2

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Kaczman, D. ; Texas Instrum., Dallas, TX ; Shah, M. ; Alam, M. ; Rachedine, M.
more authors

This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with DigRF interface that supports 10 WCDMA bands (I, II, III, IV, V, VI, VIII, IX, X, XI) and 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900). The receiver is part of a single-chip SAW-less transceiver reference platform IC for mass-market smartphones, which has been designed to meet Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The novel receiver core consists of a single-stage transconductance amplifier (TCA) with large gain control range, a current commutating passive mixer enhanced for automatic on chip IIP2 calibration with 25% duty-cycle LO injection and threshold adjust, and current-input complex Direct Coupled Filter (DCF). The low noise TCAs are designed without inductive loads to save area. A self-contained on chip automatic IIP2 calibration system with algorithm routine, implemented in firmware, is used to optimize IIP2 performance. This topology eliminates the external LNA, inter-stage SAW filter and transimpedance amplifier (TZA) in conventional WCDMA designs and results in current drain and die area savings as well as improved noise. The 25% duty-cycle LO injection, with threshold adjustment, into a current driven passive double-balanced mixer results in 3 dB additional gain, lower noise figure and lower intermodulation distortion. Large signal blocking and 1/f noise performance are improved significantly by eliminating the 0 and 180deg LO signal crossover at the mixer. The full receiver achieves 2.2 dB/2.39 dB simplex/duplex NF (with - 24.5 dBm TX leakage), > 90 dBm complex two-tone IIP2, 60 dB gain and - 1/+ 5 dBm half/full-duplex image IIP3. The receiver core consumes only 15.1 mA from a 1.5 V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 3 )

Date of Publication:

March 2009

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.