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Capacitance Oscillations in Cylindrical Nanowire Gate-All-Around MOS Devices at Low Temperatures

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2 Author(s)
Chin, S.K. ; Inst. of High Performance Comput., Singapore ; Ligatchev, V.

The effects of strong transverse confinement on cylindrical nanowire (NW) gate-all-around MOS are studied using a Schrodinger-Poisson simulator with full-quantum treatment. This letter is the first to show numerically that the gate capacitance oscillates toward the geometric limit as the gate voltage increases in the inversion regime for a n-type NW MOS; such oscillations are observed at a low temperature range of 5 K-38 K for an NW radius of 5-8 nm. These oscillating capacitance-voltage characteristics are the direct results of the severe nonuniformity of the electron density of states. In contrast to previous works that used semiclassical or quantum correction approaches, this letter demonstrates that full-quantum treatment is needed to observe these capacitance oscillations.

Published in:

Electron Device Letters, IEEE  (Volume:30 ,  Issue: 4 )