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In this paper, the details of implementation of an isolated digit recognition system using NiosII soft-core processor are presented. Mel Frequency Cepstral Coefficients (MFCC) is used for feature extraction, multi layer perceptron (MLP) is used for classification and self organized feature map (SOFM) is employed for dimensionality reduction of features. Using TIDIGITS speech data base, various MLP architectures are studied and it is found that the recognition accuracy of 100% is obtained with the least computational complexity using single layer MLP with 10 hidden nodes. MLP is trained using both BP and modified BP algorithms and it is observed that MBP is 2.62 times faster than BP with 100% recognition accuracy. The digit recognition system is implemented on Altera CycloneII FPGA using hardware/software partitioning and the following observations are made: implementation of radix-4 FFT and remaining blocks for the calculation of MFCC using universal CORDIC processor as hardware/software partitioning is dasia10psila times faster compared to the complete software implementation on NiosII processor. The hardware accelerator for the NIOSII processor for implementation of MLP increases the recognition speed by a factor of 278. The technique proposed in this paper is also applicable for other soft-core processor such as Microblaze and Picoblaze.