Designing quantum adder circuits and evaluating their error performance

With the advent of efficient quantum algorithms and technological advances, design of quantum circuits has gained importance. Minimization of the gate count and the number of gate levels are the two major objectives in quantum circuit design. The peculiar nature of quantum decoherence that leads to quantum errors mandates completion of all the quantum gate operations within a time bound, hence reduction in the gate count and the number of circuit levels leads to lowering the errors and the overall cost in quantum circuits. In this paper, we propose the design of adder circuits using CNOT and C
^k
NOT gates, with significant reduction in gate count and number of gate levels over their existing counterparts in the literature. We then present a software model for evaluating errors in quantum computing circuits and employ it for evaluating the error performance of our proposed quantum adder circuits.