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In this paper a 12-bit, 100-MSample/s current-steering CMOS D/A converter for wireless communication terminals is presented. Current steering DAC is used since, it is inherently fast and can drive the resistive load without using an output buffer. A segmented architecture is proposed to attain the required speed and accuracy. The INL and DNL of the DAC is less than 1LSB and is around 0.6 and 0.2 LSB respectively. The main objective is to reduce the effects of voltage drops (IR drops) along power supplies, which cause random errors in the design of current source. To reduce these effects of IR drops a 3-dimensional, H-shaped wiring is proposed which provides equal distribution of voltages to each current source. The DAC is implemented in a 0.18 mum CMOS technology, and operates at a low supply voltage of 1.8 V.