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One of the key challenges of embedded system design is the management and conservation of power. Static power reduction methods such as synthesis of efficient hardware and compilation for low power are applied at design time. In contrast, Dynamic Power Management (DPM) techniques leverage on the runtime characteristics to reduce power when systems are serving light workloads or are idle. Though much work has been done on profile-based CPU power management, similar efforts are relatively less for I/O devices. This paper proposes an algorithm for profile based power management of the peripherals for embedded computing systems. It enables suitable decisions for efficient operation of the peripherals considering both power and performance. The algorithm lends well for applications with both single and multiple independent peripherals.
Date of Conference: 1-3 Dec. 2008