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The Stacked Capacitor DRAM Cell and Three-Dimensional Memory

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1 Author(s)
Koyanagi, M. ; Department of Bioengineering and Robotics, Tohoku University, Japan

The author chronicles the development of the stacked three-dimensional (3D) DRAM cell, highlighting his role in solving the problems of memory data-bandwidth and forecasting a dramatic increase in memory capacity based on his current work using "super-chip" integration technology.

Published in:

Solid-State Circuits Society Newsletter, IEEE  (Volume:13 ,  Issue: 1 )

Date of Publication:

Winter 2008

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