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This brief presents an integrated switching converter with a dual-mode control scheme. A pulse-train (PT) control employing a combination of four pulse control patterns is proposed to achieve optimal regulation performance under various operation scenarios. Meanwhile, a high-frequency pulsewidth modulation (PWM) control is adopted to ensure low output ripples and avoid digital limit cycling in steady state. The converter was fabricated with a 0.35- mum digital CMOS n-well process. The entire die area, including the on-chip pads and power devices, is 1.31 mm2 . Experimental results show that, in the steady state, the output voltage is well regulated at 1.5 V with plusmn12.5-mV ripples in the PWM mode. The measured maximum efficiency is 91%, and the efficiency stays above 70% within the entire 500-mW power range. In transient measurements, with a 100% load step change from 50 to 100 mA, the output voltage of the converter settles within 345 ns due to the fast response of the PT control, with a maximum voltage variation of 164 mV. The converter functions well when the input supply voltage frequently varies between 2.2 and 3.3 V, with a line regulation of 29.1 mV/V.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:56 , Issue: 2 )
Date of Publication: Feb. 2009