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The flying-adder frequency synthesis architecture is a novel approach of generating frequencies on chip. Since its invention, it has been used in many commercial products to cope with difficult frequency generation challenges. Along the course of this architecture's evolution, various circuit- and system-level problems have been resolved. In this paper, one remaining problem related to circuit implementation, namely, the construction of the accumulator, is studied. A new scheme is proposed to achieve the flying-adder accumulation function that not only has speed advantage but also is power and area efficient. The issue related to time-average frequency and jitter is also discussed.