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Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design

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2 Author(s)
Dipanjan Sengupta ; Electr. & Comput. Eng. Dept., Univ. of British Columbia, Vancouver, BC ; Resve A. Saleh

Among the different methods of reducing power for core-based system-on-chip (SoC) designs, the voltage-island technique has gained in popularity. Assigning cores to the different supply voltages and floorplanning to create contiguous voltage islands are two important steps in the design process. We propose a new application-driven approach to voltage partitioning and island creation with the objective of reducing overall SoC power, area, and floorplanner runtime. Given an application power-state machine (PSM), we first identify the suitable range of supply voltages for each core. Then, we generate the discrete voltage assignment table using a heuristic technique. Next, we describe a methodology of reducing the large number of available choices from the voltage assignment table down to a useful set using the application PSM. We partition the cores into islands, using a cost function that gradually shifts from a power-based assignment to a connectivity-based one. Compared with previously reported techniques, a 9.4% reduction in power and 8.7% reduction in area are achieved using our approach, with an average runtime improvement of 2.4 times.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:28 ,  Issue: 3 )