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The Impact of Strain Technology on FUSI Gate SOI CMOSFET

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5 Author(s)
Wen-Kuan Yeh ; Dept. of Electr. Eng., Nat. Univ. of Kaohsiung, Kaohsiung ; Jean-An Wang ; Ming-Hsing Tsai ; Chien-Ting Lin
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In this paper, the impact of strain engineering on device performance and reliability for fully silicide gate silicon-on-insulator CMOSFET was investigated. With characterizing device's electrical property after hot carrier (HC) and positive/negative bias instability voltage stressing, we found similar enhancement on device performance but different behavior on voltage-stressing-induced device degradation for n/pMOSFETs. Related noise analysis and charge pumping techniques were used to investigate the strain-induced oxide defect which will accelerate device degradation after long-time HC voltage stressing and/or bias instability voltage stressing.

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Device and Materials Reliability, IEEE Transactions on  (Volume:9 ,  Issue: 1 )