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A Low-Complexity High-Radix RNS Multiplier

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2 Author(s)
Kouretas, I. ; Dept. of Electr. & Comput. Eng., Univ. of Patras, Patras, Greece ; Paliouras, V.

A graph-based technique is introduced for the design of a class of residue arithmetic multipliers, as well as a family of new high-radix digit adders. A proposed design technique derives simple high-radix modulo-r n multipliers by optimally selecting among the variety of introduced digit adders the ones that compose a minimal-area multiplier. The proposed technique minimizes multiplier complexity by selecting digit adders that observe the constraints imposed on the maximum values of the various intermediate digits. The proposed technique leads to significant area and time improvements over previously published architectures for practical modulus cases.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:56 ,  Issue: 11 )