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An adaptive low-complexity space-time reduced-rank processor is proposed for interference suppression in asynchronous DS code division multiple access (CDMA) systems based on a diversity-combined decimation and interpolation method. The novel design approach for the processor employs an iterative procedure to jointly optimise the interpolation, decimation and estimation tasks for reduced-rank parameter estimation. Joint iterative least squares design parameter estimators are described and low-complexity adaptive recursive least squares (RLS) algorithms for the proposed structure are developed. To design the decimation unit, the optimal decimation scheme based on the counting principle is presented and low-complexity decimation structures are proposed. Linear space-time receivers with antenna arrays based on the proposed reduced-rank processor are then presented and investigated to mitigate multi-access interference and intersymbol interference in an asynchronous DS-CDMA system uplink scenario. An analysis of the convergence properties of the proposed space-time processor is carried out and analytical expressions are derived to predict the mean squared error performance of the proposed processor with RLS algorithms. Simulations show that the proposed processor outperforms the best known reduced-rank schemes at substantially lower complexity.