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A High Speed Cu Pillar Bump Plating Process

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8 Author(s)
Yun Zhang ; Cookson Electronics, Enthone United States ; Stream Chung ; Eric Walch ; Christian Rietman
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Cu pillars have been adopted and implemented in high volume manufacturing environment as early as 2006 as a replacement for high lead bumps. It is not only lead-free, but also offers the added advantage of higher stand-off, finer pitch capability and better electromigration resistance compared to tin-lead solder bumps. Cu pillar technology promises to be one of the main interconnect technologies in advanced packaging arena together with other lead-free solder processes and Cu plated through silicone vias (TSV) in the years to come. Within wafer (WIW), within die (WID) and within feature (WIF) uniformity become increasingly important as pillar diameter, pitch size shrinks and photoresist thickness increases. There is a trade off when it comes to plating speed and uniformity. Generally speaking, when plating speed increases beyond 2 mum/min, the uniformity suffers. That is why most of the conventional plating processes are operated at 2 mum/min or below. Under certain conditions, few processes could be "stretched" to up to 3 mum/min but process window becomes rather narrow and the plating process and quality becomes difficult to control. When the photoresist (or pillar) height approaches 120 mum, it is desirable to employ a plating process that is capable of 4 mum/min or higher to increase throughput while meeting uniformity and surface roughness requirements, and producing Cu pillars with materials properties similar or superior to those obtained with conventional Cu plating processes. In this paper, we describe a high speed Cu pillar plating process that fits above description.

Published in:

2008 3rd International Microsystems, Packaging, Assembly & Circuits Technology Conference

Date of Conference:

22-24 Oct. 2008