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Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers

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5 Author(s)
Casha, O. ; Dept. of Microelectron. & Nanoelectron., Univ. of Malta, Msida ; Grech, I. ; Badets, F. ; Morche, D.
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A complete analysis of the spur characteristics of edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this brief. The novelty of this analysis is the fact that it can be used to estimate the effect of both the in-lock error and the delay-stage mismatch on the spurious level of the frequency multiplier with low computational complexity. In addition, a way to reduce the mismatch between the delay cells in the delay line is discussed via an analytic model and verified by the implementation of a delay cell in a 65-nm CMOS process.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 2 )

Date of Publication:

Feb. 2009

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