Referenced Items are not available for this document.
A complete analysis of the spur characteristics of edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this brief. The novelty of this analysis is the fact that it can be used to estimate the effect of both the in-lock error and the delay-stage mismatch on the spurious level of the frequency multiplier with low computational complexity. In addition, a way to reduce the mismatch between the delay cells in the delay line is discussed via an analytic model and verified by the implementation of a delay cell in a 65-nm CMOS process.
Published in:
Circuits and Systems II: Express Briefs, IEEE Transactions on
(Volume:56
,
Issue:
2
)
Date of Publication: Feb. 2009
- Page(s):
- 132 - 136
- ISSN :
- 1549-7747
- INSPEC Accession Number:
- 10498967
- Digital Object Identifier :
- 10.1109/TCSII.2008.2011605
- Product Type:
- Journals & Magazines
- Date of Publication :
- 13 February 2009
- Date of Current Version :
- 24 February 2009
- Issue Date :
- Feb. 2009
- Sponsored by :
- IEEE Circuits and Systems Society
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