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Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

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3 Author(s)
Tajalli, A. ; Microelectron. Syst. Lab. (LSM), Swiss Fed. Inst. of Technol. (EPFL), Lausanne ; Alioto, M. ; Leblebici, Y.

This brief presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. Based on the proposed approach, a source-follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18-mum CMOS technology show an improvement by a factor of as high as 2.4 in power-delay product (PDP). It is also shown that the proposed technique can be used for implementing subthreshold ultra-low power SCL logic gates with a better power and area efficiency, compared to the traditional SCL subthreshold circuits. An optimized approach is proposed to improve the power efficiency of ultra-low power STSCL library cells.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 2 )

Date of Publication:

Feb. 2009

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