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This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13-??m CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 dB and a peak spurious-free dynamic range of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within ??0.30 LSB and ??0.95 LSB, respectively. The ADC occupies an active die area of 0.56 mm2 and consumes 51.6 mW at a 1.2 V power supply.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:56 , Issue: 5 )
Date of Publication: May 2009