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A Methodology for Mapping SysML Activity Diagram to Time Petri Net for Requirement Validation of Embedded Real-Time Systems with Energy Constraints

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4 Author(s)
Andrade, E. ; Inf. Center (CIn), Fed. Univ. of Pernambuco (UFPE), Recife ; Maciel, P. ; Callou, G. ; Nogueira, B.

In this paper we use the Activity diagram of the System Modeling Language (SysML) in combination with the new UML profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) in order to validate functional, timing and low power requirements in early phases of the embedded system development life-cycle. However, SysML lacks a formal semantics and hence it is not possible to apply, directly, mathematical techniques on SysML models for system validation. Thus, a novel approach for automatic translation of SysML Activity diagram into Time Petri Net with Energy constraints (ETPN) is proposed. In order to depict the practical usability of the proposed method, a case study is presented, namely, pulse-oximeter. Besides, the estimates obtained (execution time and energy consumption) from the model are 95% close to the respective measures obtained from the real hardware platform.

Published in:

Digital Society, 2009. ICDS '09. Third International Conference on

Date of Conference:

1-7 Feb. 2009